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19-2718; Rev 0; 1/03
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2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier
General Description
The MAX3882 is a deserializer combined with clock and data recovery and limiting amplifier ideal for converting 2.488Gbps/2.67Gbps serial data to 4-bit-wide, 622Mbps/667Mbps parallel data for SDH/SONET applications. The device accepts serial NRZ input data as low as 10mVP-P of 2.488Gbps/2.67Gbps and generates four parallel LVDS data outputs at 622Mbps/667Mbps. Included is an additional high-speed serial data input for system loopback diagnostic testing. For data acquisition, the MAX3882 does not require an external reference clock. However, if needed, the loopback input can be connected to an external reference clock of 155MHz/167MHz or 622MHz/667MHz to maintain a valid clock output in the absence of input data transitions. Additionally, a TTL-compatible loss-of-lock output is provided. The device provides a vertical threshold adjustment to compensate for optical noise generated by EDFAs in WDM transmission systems. The MAX3882 operates from a single +3.3V supply and consumes 610mW. The MAX3882's jitter performance exceeds all SDH/ SONET specifications. The device is available in a 6mm 6mm 36-pin QFN package.
Features
o No Reference Clock Required for Data Acquisition o Input Data Rates: 2.488Gbps or 2.67Gbps o Fully Integrated Clock and Data Recovery with Limiting Amplifier and 1:4 Demultiplexer o Parallel Output Rate: 622Mbps/667Mbps o Differential Input Range: 10mVP-P to 1.6VP-P without Threshold Adjust o Differential Input Range: 50mVP-P to 600mVP-P with Threshold Adjust o 0.65UI High-Frequency Jitter Tolerance o Loss-of-Lock (LOL) Indicator o Wide Input Threshold Adjust Range: 170mV o Maintain Valid Clock Output in Absence of Data Transitions o System Loopback Input Available for System Diagnostic Testing o Operating Temperature Range -40C to +85C o Low Power Dissipation: 610mW at +3.3V
MAX3882
Ordering Information
PART MAX3882EGX TEMP RANGE -40oC to +85oC PINPACKAGE 36 QFN PKG CODE G3666-1
Applications
SDH/SONET Receivers and Regenerators Add/Drop Multiplexers Digital Cross-Connects SDH/SONET Test Equipment DWDM Transmission Systems
Pin Configuration
VCTRL CAZ+
CAZ-
VREF
VCC
VCC
TOP VIEW
FREFSET
29
36
35
34
33
32
31
30
28 27 26 25 24
VCC_OUT
RATESET
GND VCC SDI+ SDIVCC SLBI+ SLBISIS LOL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
PD3+ PD3PD2+ PD2GND PD1+ PD1PD0+ PD0-
MAX3882
23 22 21 20 19
LREF
VCC_OUT
VCC_VCO
VCC_VCO
GND
GND
FIL
PCLK-
QFN
________________________________________________________________ Maxim Integrated Products
PCLK+
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
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2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier MAX3882
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC ................................................-0.5 to +5.0V Input Voltage Levels (SDI+, SDI-, SLBI+, SLBI-) ...........(VCC - 1.0V) to (VCC + 0.5V) Input Current Levels (SDI+, SDI-, SLBI+, SLBI-)..............20mA LVDS Output Voltage Levels (PCLK, PD_).......................................-0.5V to (VCC + 0.5V) Voltage at LOL, RATESET, SIS, LREF, VREF, FIL, CAZ+, CAZ-, VCTRL, FREFSET ..........................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85C) 36-Lead QFN (derate 32.4mW/C above +85C) .......830mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0 to +3.6V, TA = -40C to +85C. Typical values are at +3.3V and at TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Supply Current Single-Ended Input Voltage Range Input Common-Mode Voltage Range Input Termination to VCC Differential Input Voltage Range with Threshold Adjust Enabled SDI+, SDIThreshold Adjustment Range Threshold-Control Voltage Threshold-Control Linearity Threshold Setting Accuracy Threshold Setting Stability VREF Voltage Output LVDS Output High Voltage LVDS Output Low Voltage LVDS Differential Output Voltage LVDS Change in Magnitude of Differential Output Voltage for Complementary States LVDS Offset Output Voltage LVDS Change in Magnitude of Output Offset Voltage for Complementary States LVDS Differential Output Impedance VOS VOH VOL VOD 0.925 250 400 Figure 2 15mV |VTH| 80mV 80mV < |VTH| 170mV RL = 50k -18 -6 -12 2.14 2.2 VTH VCTRL RIN Figure 2 Figure 2 (Note 2) SYMBOL ICC VIS Figure 1 Figure 1 VCC 0.8 VCC 0.4 42.5 100 -170 0.302 5 +18 +6 +12 2.24 1.475 50 CONDITIONS MIN TYP 185 MAX 230 VCC + 0.4 VCC 57.5 600 +170 2.097 UNITS mA V V mVP-P mV V % mV mV V V V mV
VOD 1.125
25 1.275 25
mV V mV
80
120
2
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2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0 to +3.6V, TA = -40C to +85C. Typical values are at +3.3V and at TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER LVDS Output Current LVTTL Input High Voltage LVTTL Input Low Voltage LVTTL Input Current LVTTL Output High Voltage LVTTL Output Low Voltage VOH VOL IOH = +20A IOL = -1mA VIH VIL -10 2.4 0.4 SYMBOL CONDITIONS Short together or short to GND 2.0 0.8 +10 MIN TYP MAX 12 UNITS mA V V A V V
MAX3882
Note 1: At -40C, DC characteristics are guaranteed by design and characterization. Note 2: Voltage applied to VCTRL pin is from 0.302V to 2.097V when input threshold is adjusted from +170mV to -170mV.
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0 to +3.6V, TA = -40C to +85C. Typical values are at +3.3V and at TA = +25C, unless otherwise noted.) (Note 3)
PARAMETER Serial Input Data Rate Differential Input Voltage Threshold Adjust Disabled SDI+, SDIDifferential Input Voltage SLBI+, SLBIJitter Peaking Jitter Transfer Bandwidth Sinusoidal Jitter Tolerance JP JBW f = 100kHz f = 1MHz f = 10MHz Sinusoidal Jitter Tolerance with Threshold Adjust Enabled (Note 5) Jitter Generation Differential Input Return Loss Tolerated Consecutive Identical Digits Acquisition Time LOL Assert Time Low-Frequency Cutoff for DC Offset-Cancellation Loop JGEN 20log|S11| f = 100kHz f = 1MHz f = 10MHz (Note 6) 100kHz to 2.5GHz 2.5GHz to 4.0GHz BER = 10-10 (Note 7) Figure 4 Figure 4 CAZ = 0.1F 2.3 4 3.1 0.62 0.44 f 2MHz 1.7 4.1 1.0 0.6 4.1 0.75 0.41 2.7 17 15 2000 1.0 100.0 psRMS dB Bits ms s kHz UIP-P UIP-P SYMBOL RATESET = 0 RATESET = 1 VID (Note 4) Figure 1 10 CONDITIONS MIN TYP 2.488 2.667 1600 MAX UNITS Gbps
mVP-P
50
800 0.1 2.0
mVP-P dB MHz
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2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier MAX3882
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0 to +3.6V, TA = -40C to +85C. Typical values are at +3.3V and at TA = +25C, unless otherwise noted.) (Note 3)
PARAMETER SYMBOL CONDITIONS FREFSET = VCC, RATESET = GND Reference Clock Frequency RATESET = VCC FREFSET = GND, RATESET = GND RATESET = VCC Reference Clock Accuracy VCO Frequency Drift Data Output Rate Clock Output Frequency Output Clock-to-Data Delay Clock Output Duty Cycle Clock and Data Output Rise/Fall Time LVDS Differential Skew LVDS Channel-to-Channel Skew tR , tF tSKEW1 tSKEW2 20% to 80% Any differential pair PD_ TCK-Q (Note 8) RATESET = 0 RATESET = 1 RATESET = 0 RATESET = 1 (Note 9) -80 45 100 50 MIN TYP 155 167 622 667 100 400 622 667 622 667 +80 55 250 50 100 ppm ppm Mbps MHz ps % ps ps ps MHz MAX UNITS
Note 3: AC characteristics are guaranteed by design and characterization. Note 4: Jitter tolerance is guaranteed (BER 10-10) within this input voltage range. Input threshold adjust is disabled when VCTRL is connected to VCC. Note 5: Measured with the input amplitude set at 100mVP-P differential swing with a 20mV offset and an input edge speed of 145ps (4th-order Bessel filter with f3dB = 1.8GHz). Note 6: Measured with 10mVP-P OC-48 differential input with PRBS 223 - 1 and BW = 12kHz to 20MHz. Note 7: Measured at OC-48 data rate using a 0.068F loop-filter capacitor. Note 8: Under LOL condition, the CDR clock output is set by the external reference clock. Note 9: Relative to the falling edge of PCLK+. See Figure 3.
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2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
RECOVERED CLOCK AND DATA (INPUT = 2.488Gbps, 223 - 1 PATTERN, VIN = 10mVP-P)
MAX3882 toc01
MAX3882
SUPPLY CURRENT vs. TEMPERATURE
250 240 SUPPLY CURRENT (mA) 230 220 210 200 190 180 170 160 0.1 -50 -25 0 25 50 75 100 10
MAX3882 toc02
JITTER TOLERANCE (2.48832Gbps, 223 - 1 PATTERN, VIN = 16mVP-P WITH ADDITIONAL 0.15UI DETERMINISTIC JITTER)
MAX3882 toc03
260
100
JITTER TOLERANCE (UIP-P)
10
200mV/div
1 BELLCORE MASK
500ps/div
100
1k
10k
TEMPERATURE (C)
JITTER FREQUENCY (Hz)
JITTER TOLERANCE vs. INPUT AMPLITUDE (2.48832Gbps, 223 - 1 PATTERN, WITH ADDITIONAL 0.15UI DETERMINISTIC JITTER)
MAX3882 toc04
JITTER TRANSFER
MAX3882 toc05
PARALLEL CLOCK OUTPUT JITTER
fCLK = 622.08MHz TOTAL WIDEBAND RMS JITTER = 2.720ps PEAK-TO-PEAK JITTER = 20.80ps
MAX3882 toc06
0.6 0.5 JITTER TOLERANCE (UIP-P) JITTER FREQUENCY = 10MHz 0.4 0.3 0.2 0.1 0 1 10 100 1000
5 0 -5 TRANSFER (dB) -10 -15 -20 -25 -30 -35 -40 BELLCORE MASK
10,000
1
10
100
1000
10,000
20ps/div
INPUT AMPLITUDE (mVP-P)
JITTER FREQUENCY (kHz)
BIT-ERROR RATE vs. INPUT AMPLITUDE
MAX3882 toc07
PULLIN RANGE (RATESET = 0)
2.9 2.8 FREQUENCY (GHz) 2.7 2.6 2.5 2.4 2.3 2.2
MAX3882 toc08
1.00E-04 1.00E-05 BIT-ERROR RATIO 1.00E-06 1.00E-07 1.00E-08 1.00E-09 1.00E-10 1.00E-11 1 2 3 4 5 INPUT VOLTAGE (mVP-P)
3.0
2.1 2.0 -40 -15 10 35 60 85 AMBIENT TEMPERATURE (C)
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2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier 1MAX3882
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
JITTER TOLERANCE vs. VCTRL (2.67Gbps, 223 - 1 PATTERN, VIN = 100mVP-P)
MAX3882 toc09
S11
MAX3882 toc10
0.7 SINUSOIDAL JITTER TOLERANCE (UIP-P) 0.6 0.5
INPUT FILTERED WITH AN 1870MHz FILTER
20 10 0
0.4 dB 0.3 0.2 0.1 JITTER FREQUENCY = 5MHz 0 1.05 1.10 1.15 1.20 1.25 1.30 VCTRL (V) -40 0 500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (MHz) -20 -30 -10
Pin Description
PIN 1, 11, 16, 23 2, 5, 31, 32 3 4 6 7 8 9 10 12, 14 13 15, 28 17 18 19 20 21 22 NAME GND VCC SDI+ SDISLBI+ SLBISIS LOL LREF VCC_VCO FIL VCC_OUT PCLKPCLK+ PD0PD0+ PD1PD1+ Supply Ground +3.3V Supply Voltage Positive Data Input. 2.488Gbps/2.67Gbps serial data stream, CML. Negative Data Input. 2.488Gbps/2.67Gbps serial data stream, CML. Positive System Loopback Input or Positive Reference Clock Input, CML Negative System Loopback Input or Negative Reference Clock Input, CML Signal Input Selection, LVTTL. Low for normal data, high for system loopback. Loss-of-Lock Output, LVTTL, Active Low TTL Control Input for PLL Clock Holdover. Low for PLL lock to reference clock, high for PLL lock to input data. Supply Voltage for the VCO PLL Loop-Filter Capacitor Input. Connect a 0.068F loop-filter capacitor between FIL and VCC_VCO. Supply Voltage for LVDS Output Buffers Negative Clock Output, LVDS Positive Clock Output, LVDS Negative Data Output, LVDS Positive Data Output, LVDS Negative Data Output, LVDS Positive Data Output, LVDS FUNCTION
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2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier
Pin Description (continued)
PIN 24 25 26 27 29 30 33 34 35 36 EP NAME PD2PD2+ PD3PD3+ RATESET FREFSET CAZ+ CAZVREF VCTRL Negative Data Output, LVDS Positive Data Output, LVDS Negative Data Output, LVDS, MSB Positive Data Output, LVDS, MSB Sets the VCO frequency. LVTTL low for 2.488Gbps operation, high for 2.67Gbps operation. Sets Reference Frequency. LVTTL low for 622MHz/667MHz reference, high for 155MHz/167MHz reference. Positive Capacitor Input for DC Offset-Cancellation Loop. Connect a 0.1F capacitor between CAZ+ and CAZ-. Negative Capacitor Input for DC Offset-Cancellation Loop. Connect a 0.1F capacitor between CAZ+ and CAZ-. 2.2V Bandgap Reference Voltage Output. Optionally used for threshold adjustment. Analog Control Input for Threshold Adjustment. Connect to VCC to disable threshold adjust. FUNCTION
MAX3882
Ground. The exposed pad must be soldered to the circuit board ground for proper thermal and Exposed Pad electrical performance.
Detailed Description
The MAX3882 deserializer with clock and data recovery and limiting amplifier converts 2.488Gbps/2.67Gbps serial data to clean 4-bit-wide, 622Mbps/667Mbps LVDS parallel data. The device combines a limiting amplifier with a fully integrated phase-locked loop (PLL), data retiming block, 4-bit demultiplexer, clock divider, and LVDS output buffer (Figure 5). The PLL consists of a phase/frequency detector (PFD), loop filter, and voltagecontrolled oscillator (VCO). The MAX3882 is designed to deliver the best combination of jitter performance and power dissipation by using a fully differential signal architecture and low-noise design techniques. The input signal to the device (SDI) passes through a DC offset control block, which balances the input signal to a zero crossing at 50%. The PLL recovers the serial clock from the serial input data stream and produces the properly aligned data and the buffered recovered clock. The frequency of the recovered clock is divided by four and converted to differential LVDS parallel output PCLK. The demultiplexer generates 4-bit-wide 622Mbps/667Mbps parallel data.
low as 4mV P-P for a BER of 10 -10. The MAX3882 is designed to directly interface with a transimpedance amplifier (MAX3277). For applications when vertical threshold adjustment is needed, the MAX3882 can be connected to the output of an AGC amplifier (MAX3861). Here, the input voltage range is 50mV P-P to 600mV P-P . See the Design Procedure section for decision threshold adjust.
Phase Detector
The phase detector in the MAX3882 produces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming.
Frequency Detector
The digital frequency detector (FD) acquires frequency lock without using an external reference clock. The frequency difference between the received data and the VCO clock is derived by sampling the in-phase and quadrature VCO outputs on both edges of the data input signal. Depending on the polarity of the frequency difference, the FD drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the FD returns to a neutral state. False locking is eliminated by this digital frequency detector.
Input Amplifier
The SDI inputs of the MAX3882 accept serial NRZ data at 2.488Gbps/2.67Gbps with 10mVP-P to 1600mVP-P amplitude. The input sensitivity is 10mVP-P, at which the jitter tolerance is met for a BER of 10 -10 when the threshold adjust is not used. The input sensitivity is as
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2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier MAX3882
VCC + 0.4V 5mV 800mV VCC +188 +170 +152 VCC - 0.4V (a) AC-COUPLED SINGLE-ENDED INPUT VCC 800mV VCC - 0.4V -170 -188 VCC - 0.8V (b) DC-COUPLED SINGLE-ENDED INPUT THRESHOLD-SETTING STABILITY (OVER TEMPERATURE AND POWER SUPPLY) 1.3 5mV 0.3 1.1 2.1 VCTRL (V) THRESHOLD-SETTING ACCURACY (PART-TO-PART VARIATION OVER PROCESS) VTH (mV)
-152
Figure 1. Definition of Input Voltage Swing
Figure 2. Relationship Between Control Voltage and Threshold Voltage
tCK PCLK+ tCK-Q (PD+) - (PD-)
LOL OUTPUT INPUT DATA
2.488Gbps PRBS 223 - 1
2.488Gbps PRBS 223 - 1
LOL ASSERT TIME
ACQUISITION TIME
Figure 3. Definition of Clock-to-Q Delay
Figure 4. LOL Assert Time and PLL Acquisition Time Measurement
VCO Tuning Range
The MAX3882 can operate at both OC-48 and OC-48 with FEC data rates. Select the data frequency using the RATESET pin.
Loop Filter and VCO
The fully integrated PLL has a second-order transfer function, with a loop bandwidth (fL) fixed at.1.7MHz. An external capacitor between VCC_VCO and FIL sets the damping of the PLL. All jitter specifications are based on the CFIL capacitor being 0.068F. Note that the PLL jitter transfer bandwidth does not change as the external capacitor changes, but the jitter peaking, acquisition time, and loop stability are affected.
8
For an overdamped system (fZ / fL) < 0.25, the jitter peaking (JP) of a second-order system can be approximated by: JP = 20log(1 + fZ / fL) The PLL zero frequency (fZ) is a function of the external capacitor (CFIL) and can be approximated according to: fZ = 1 / 2(650)CFIL Figures 6 and 7 show the open-loop and closed-loop transfer functions. The PLL acquisition time is also directly proportional to the external capacitor CFIL.
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2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier
Loss-of-Lock Monitor
The LOL output indicates a PLL lock failure, either due to excessive jitter present at data input or due to loss of input data. In the case of loss of input data, the LOL indicates a loss-of-signal condition. The LOL output is asserted low when the PLL loses lock.
Applications Information
Clock Holdover Capability
Clock holdover is required in some applications where a valid clock needs to be provided to the upstream device in the absence of data transitions. To provide this function, an external reference clock rate of 155MHz/167MHz or 622MHz/667MHz must be applied to the SLBI input. Control input FREFSET selects which reference clock rate to use. The control LREF selects whether the PLL locks to the input data stream (SDI) or the reference clock (SLBI). When LREF is low, the input is switched to the reference clock input. This LREF input can be driven by connecting the LOL output pin directly or connecting to any other power monitor signal from the system.
MAX3882
Output LVDS Interface: PD, PCLK
The MAX3882's clock and data outputs are LVDS compatible to minimize power dissipation, speed transition time, and improve noise immunity. These outputs comply with the IEEE LVDS specification. The differential output signal magnitude is 250mV to 400mV.
Design Procedure
The MAX3882 provides a differential output clock (PCLK). Table 1 shows the pin configuration for choosing the type of operation mode.
System Loopback
The MAX3882 is designed to allow system loopback testing. The user can connect the serializer output (MAX3892) directly to the SLBI inputs of the MAX3882 for system diagnostics. See Table 1 for selecting the system loopback operation mode. During system loopback, LOL cannot be connected to LREF.
Decision Threshold Adjust
Decision threshold adjust is available for WDM applications where optical amplifiers are used, generating spontaneous optical noise at data logic high. The decision threshold adjust range is 170mV. Use the provided 2.2V bandgap reference VREF pin or an outside source, such as an output from a DAC to control the threshold voltage. The +170mV to -170mV threshold offset can be accomplished by varying the VCTRL voltage from 0.3V to 2.1V, respectively. See Figure 2. When using the VREF to generate voltage for threshold setting, see Figure 8. Connect VCTRL directly to VCC to disable threshold adjust.
Interfacing the MAX3882
To correctly interface with the MAX3882's CML input and LVDS outputs, refer to Maxim Application Note HFAN-1.0: Interfacing Between CML, PECL, and LVDS.
DC-Offset Cancellation Loop Filter
A DC-offset cancellation loop is implemented to remove the DC offset of the limiting amplifier. To minimize the low-frequency pattern-dependent jitter associated with this DC-cancellation loop, the low-frequency cutoff is 10kHz typical with CAZ = 0.1F, connected across CAZ+ and CAZ-.
Table 1. Operation Modes
FREFSET X X X X 1 1 0 0 LREF 1 1 1 1 0 0 0 0 SIS 0 0 1 1 X X X X RATESET 0 1 0 1 0 1 0 1 OPERATION MODE DESCRIPTION Normal operation: PLL locked to data input at 2.488Gbps Normal operation: PLL locked to data input at 2.67Gbps System loopback: PLL lock frequency at 2.488Gbps System loopback: PLL lock frequency at 2.67Gbps Clock holdover: PLL locked to reference frequency at 155MHz Clock holdover: PLL locked to reference frequency at 167MHz Clock holdover: PLL locked to reference frequency at 622MHz Clock holdover: PLL locked to reference frequency at 667MHz
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2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier MAX3882
CAZ CAZ+ CAZ-
PDO+ VREF BANDGAP REFERENCE LVDS
MAX3882
0 1
PDOPD1+
SDI+ AMP SDIVCTRL
DC OFFSET CANCELLATION
DQ CK
LVDS 4-BIT DEMULTIPLEXER LVDS PD2PD1PD2+
SLBI+ AMP SLBIPFD LREF SIS FREFSET LOGIC PLL FIL LOL VCC RATESET LPF VCO DIV/4 LVDS LVDS
PD3+ PD3-
PCLK+ PCLK-
Figure 5. Functional Diagram
HO(j2f) (dB)
HO(j2f) (dB) 0 -3
CFIL = 0.01F
OPEN-LOOP GAIN
CLOSED-LOOP GAIN
CFIL = 0.068F
CFIL = 0.068F fZ = 3.6kHz
CFIL = 0.01F fZ = 2.45kHz
f = (kHz) 1 10 100 1000
f = (kHz) 1 10 100 1000
Figure 6. Open-Loop Transfer Function
Figure 7. Closed-Loop Transfer Function
Layout Techniques
For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled-impedance transmission lines to interface with the MAX3882 high-speed inputs and outputs. Power-supply decoupling should be placed as close to the VCC as possible. To reduce feedthrough, isolate input signals from output signals.
10
Exposed Pad Package
The exposed pad, 36-pin QFN incorporates features that provide a very low thermal-resistance path for heat removal from the IC. The pad is electrical ground on the MAX3882 and should be soldered to the circuit board for proper thermal and electrical performance.
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2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier MAX3882
+3.3V
0.068F
-3.3V
155MHz CLOCK
SIS RATESET
FIL
VCC
LREF
LOL PD3+ 100* VCC
SLBI+ SLBI-
PD3-
PD2+
MAX3882
0.1F SDI+ TIA OUTPUT AGC SDI0.1F VCTRL PD1PD1+ PD2-
100*
100*
OVERHEAD TERMINATION
MAX3861
R2
R1 VREF PD0+ R1 + R2 50k PD0100*
PCLK+ 100* FREFSET CAZ+ CAZPCLK-
+3.3V
0.1F
*REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION. THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50.
Figure 8. Connecting the MAX3882 with Threshold Adjust and Clock Holdover Enabled
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2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier MAX3882
Typical Application Circuit
+3.3V
0.068F SYSTEM LOOPBACK SIS +3.3V SLBI+ 0.01F SLBIPD2+ PD3RATESET FIL VCC LREF LOL PD3+ 100* VCC
MAX3882
0.1F SDI+ TIA SDI0.1F VCTRL PD1+ PD2-
100*
100* PD1-
OVERHEAD TERMINATION
MAX3277
VREF
PD0+ 100* PD0+3.3V PCLK+ 100* PCLKFREFSET CAZ+ CAZ-
0.1F *REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION. THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50.
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2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 36L,40L, QFN.EPS
MAX3882
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2.488Gbps/2.67Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier MAX3882
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
U
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 14 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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